1. As AI data centers' computing power demands continue to climb, traditional copper interconnect technology is approaching its physical limits. Co-packaged optics (CPO) is being touted as a key interconnect solution for next-generation AI infrastructure. However, just as Taiwan Semiconductor Manufacturing Co. (TSMC) prepares to mass-produce chips using its COUPE platform in 2026, a long-overlooked step in the process is becoming a critical bottleneck across the entire supply chain: testing.
2. According to a recent research report from market research firm TrendForce, the inspection and testing phase for CPO chips currently lacks a unified industry standard and relies heavily on manual operations. This makes it one of the primary bottlenecks limiting large-scale CPO chip production. A 100% inspection of a single photonic integrated circuit (PIC) chip takes an average of over 100 seconds, which is far less efficient than traditional chip testing.
3. CPO technology integrates optical components into a PIC, which is then co-packaged with an electronic integrated circuit (EIC) inside a single chip. This replaces electrical pathways with optical ones to reduce power consumption and latency. The combined EIC-PIC unit is known as an optical engine (OE). While traditional EIC testing is purely electrical, a PIC contains numerous optical components—such as couplers, modulators, photodetectors, optical filters, and waveguides. Testing an OE requires expertise in three domains simultaneously: electrical, optical, and electro-optical interaction, making it far more complex than conventional chip testing.
4. PIC testing involves measuring parameters like insertion loss (IL), polarization-dependent loss (PDL), responsivity, waveguide propagation loss, and optical crosstalk. Currently, there are no unified test standards for these measurements.
5. A more specific physical challenge lies in the precise alignment of optical probes. The process of guiding external light from an optical fiber into an OE's waveguide is called optical coupling. The cross-sectional area of a single-mode fiber core is approximately 78.5 square micrometers, while that of a waveguide is only about 0.099 square micrometers—a difference of nearly 800 times. Without nanometer-scale alignment accuracy, coupling losses are enormous. The fiber array must maintain a precise distance from the wafer or chip surface while fine-tuning the angle relative to the coupler to maximize optical power transmission, before sequentially scanning different wavelength ranges. This entire operation currently remains a manual process.
6. A CPO chip goes through four testing stages from wafer to system. Stage one is PIC wafer-level testing (OWAT), including basic DC electrical and optical tests. Stage two is EIC-PIC wafer-level testing, involving modulation function and high-speed tests. Stage three is OE-level testing, a critical phase for full-process calibration and identifying "known good optical engines" (KGOEs). Stage four is advanced packaging module-level testing for full-system functional verification.
7. Among these, the first stage—PIC wafer-level testing—is the most critical. PICs are typically manufactured using mature process nodes, while EICs use advanced, more costly processes. Screening out defective wafers during the PIC stage, before they are bonded to EICs, prevents the waste of expensive EICs and significantly reduces downstream processing losses.
8. The CPO test equipment market is accelerating, with a clear trend of consolidation between traditional automated test equipment (ATE) giants and specialized optical test firms.
9. Two major EIC test equipment leaders—Japan's Advantest and the U.S.'s Teradyne—are both partnering with optical probe specialists to fill their capability gaps. Advantest’s strategy involves a partnership with FormFactor. In June 2024, Advantest collaborated with Jenoptik and Ayar Labs to introduce the UFO probe card, which integrates both electrical and optical probes on a single card to enable simultaneous electro-optical testing. Its core innovation is an alignment tolerance compensation technology. In April 2025, the two companies further unveiled the V93000-Triton photonic test system, equipped with 9-axis photon alignment capabilities and FormFactor's OptoVue Pro optical alignment system.
10. Teradyne is pursuing a dual approach of acquisition and partnership. In 2025, Teradyne acquired Quantifi Photonics and entered a partnership with Germany's ficonTEC (now a subsidiary of China's Robo Technik). In March 2025, the partners jointly launched the industry's first high-yield 300mm dual-side wafer probe test system. ficonTEC provides the WLT-D2 dual-side wafer testing platform, which offers precision alignment within a 50 nanometer range. This allows for simultaneous electrical testing on the wafer's top side and optical testing on its bottom side.
11. Keysight, a global leader in measurement instruments, also offers a complete PIC wafer testing solution and is integrated with FormFactor. Its N778x series of polarization synthesizers can quickly switch between different polarization states. When used with the N7700100C Polarization Lambda Scan software, it derives parameters like IL and PDL using a matrix method, significantly boosting testing efficiency.
12. Chroma is a global leader in system-level test (SLT) equipment. Its photodiode aging and reliability test systems, Models 58604, 58604-C, and 58606 series, are designed specifically for the reliability testing of PIC components. Chroma has announced it will apply its optical testing expertise from the SLT stage to developing CPO test equipment.
13. In September 2025, Enlitech, in collaboration with iST, launched the Night Jar silicon photonics chip testing platform. This is an add-on hyperspectral imaging analysis system that can be directly installed on any brand of probe station and is suitable for various testing stages. Night Jar can precisely locate the position of light leakage and measure quantitative IL values for specific waveguide sections or optical components, enabling wafer-level optical loss mapping. This helps R&D teams identify defects more quickly and accurately.
14. As chip designs grow more complex, the number of required test stations and total test time per chip is increasing, leading to a rising share of test equipment in semiconductor capital expenditure. With CPO chips being added to product portfolios, this share is expected to climb even higher. Looking at the equipment vendor landscape, traditional ATE giants are rapidly bolstering their optical capabilities through mergers and partnerships, while Keysight, Chroma, and Enlitech are carving out positions in their respective niches. The entire supply chain is reorganizing around the demands of CPO testing.
Source:
https://finance.biggo.com/news/cLuMzJ0BNZYCTTDvPB54
